Printed Circuit Boards (PCB) are the current mainstay for virtually all integrated circuit assembly and packaging today for computers, laptops, cell phones, cameras, TVs, appliances, avionics, etc. However new high speed and high density circuit technologies are emerging which will severely impact PCB performance. As Moore's Law for integrated circuits continues to scale toward smaller transistor sizes, the results are higher clock rate frequencies and increased functionality as more transistors are packed into ever smaller areas. Consequently, new integrated circuit inputs and outputs (I/O) are physically smaller, are much closer together in spacing (called pitch), can be either RF, DC, analog or digital, and operate at much higher data rates and higher frequencies.
Current PCB materials and construction methods are not scalable for the smaller geometries and higher densities of the new integrated circuits and are inadequate as the clock rates approach 100 Gigabits per second (Gb/s). Presently, PCB high speed digital and RF interconnects are implemented as transmission lines; either microstrip or stripline to control the impedance (usually 50 ohms) These lines are manufactured using metal foil bonded to organic substrate or dielectric material using: (i) glass-reinforced epoxy laminate sheets (called FR-4); or (ii) polytetrafluoroethylene (trade name is called Teflon); or (iii) a flexible material such as polyimide; or (iv) a combination of thereof. Patterns are etched into the foil to form interconnects and vias are drilled and plated. To make multilayer PCB, subsequent sheets are processed similarly and finally all the respective layers are bonded together using heat and pressure to form a signal multilayer PCB. The final step in the process is to plate the top and bottom surfaces with a material suitable for assembly (gold or solder) and then coated with a material to seal the inner layers and provide a solder stop or resist.
As a function of Moore's Law, integrated circuits continue grow in the number of transistors per chip and proportionately need more I/O for a given chip. The effect of more I/O in a given area causes the pitch of the contacts of the I/O to be smaller. The construction methods of PCB by etching foil bonded to organic materials is limited in how small the interconnects can be patterned. Another limitation is the via size needed to route a signal from one layer of the PCB to another layer. In addition to the size of the via, minimum spacing rules between the vias and the conductive ‘capture pads’ around the vias increases the trace-to-trace pitch achievable with PCB technologies. Also, multiple rows of vias are necessary for optimal trace-to-trace isolation. Multiple layers are needed for all the I/O to “escape” the small area of the chip and be routed to other destinations on the PCB. The more signal interconnects needed result in more layers and a thicker PCB. The thicker a PCB is, the bigger the via is, since a bigger drill bit is needed to drill through thicker PCB materials. The bigger vias cause congestion in the interconnects around the chip I/O escape area which also degrades performance.
Due to these construction methods, PCB signal interconnects are in direct contact with the dielectric material and thus a major source of signal loss, especially at higher data rates and RF frequencies (called dielectric loss). Another source of higher frequency loss is due to the skin effects of the metal foil interconnects; the surface roughness of the interconnect causes signal loss to electromagnetic wave propagation (called skin effect loss). Moreover, the skin effects are most severe at the bottom of the metal interconnect trace as the copper foil must have a certain amount of surface roughness to ensure adequate bonding strength to the PCB substrate material. Bigger vias (as described above) are another source of loss in the signal (called a discontinuity).
Another major problem with PCB materials and construction techniques is the isolation or crosstalk between two adjacent digital signal interconnects. Crosstalk is when the energy content of one signal (sometimes referred to as the “offender” line) is transferred onto a different signal (called the “victim”) and causing signal degradation or a bit error of the victim. As the data rates increase to 100 Gb/s the frequency content of the signal also increases which makes it easier for the offender data lines to contaminate the victim digital data lines. The crosstalk problem becomes quite acute as the pitch of signal interconnects becomes closer together.
PCB interfaces are connections and contactors that serve to make or break between: (i) two different PCBs; (ii) a PCB and a cable; (iii) a PCB and a test interface unit; and (iv) test interface unit to a device under test (DUT). A DUT may typically be one or more semiconductor die on a wafer or removed from a wafer. For each of these interfaces, the contactors must take different form factors to serve the application. For example, PCB-to-PCB interface might require just a few mating cycles for a given mean time between failure (MTBF). A PCB-to-cable will require a higher number of mating cycles between failure. And finally a test interface unit will have a specified number of make-break cycles of the contactors. All of the contactors interfaces are inadequate for 100 Gb/s (loss and crosstalk performance) or are limited in very high signal density as a function of very small pitches demanded by new semiconductors.
Thus, it would be an advancement to the art to provide a high density interconnect that can scale to the small geometries of the integrated circuit and provide a low loss medium and provide very high isolation as the speed of the semiconductor approach 100 Gb/s as well as providing methods of their manufacture.